Recent progress of a semiconductor manufacturing technology is extremely remarkable, and semiconductor devices with a minimum feature size of 40 nm are mass-produced. Such scaling of semiconductor devices is realized by rapid progress of a micro-patterning technology such as a mask process technology, a photolithography technology, and an etching technology. In the generation in which a pattern size is sufficiently large, a plane shape of an integrated circuit pattern that needs to be formed on a wafer is directly written as a design pattern and a mask pattern faithful to the design pattern is manufactured. Then, the manufactured mask pattern is transferred onto the wafer by projection optics, and a pattern approximately the same as the design pattern is formed on the wafer by etching a base with resist as a processing target film.
However, with the progress of scaling of an integrated circuit pattern, it has become difficult to faithfully form a pattern in each process. Consequently, a problem arises in that final finished dimensions do not become as a design pattern. Specially, in the lithography process or the etching process that is the most important process for achieving micro-patterning, patterns arranged around a pattern that needs to be formed greatly affect the dimensional accuracy of the pattern that needs to be formed.
In order to avoid such influence, technologies, such as the OPC (Optical Proximity Correction) and the PPC (Process Proximity Correction), are developed. In these technologies, an auxiliary pattern is added in advance or a width of a pattern is thickened or thinned so that a shape of a processed integrated circuit pattern becomes a design pattern (desired value).
Moreover, development of an OPC verifying technology has been progressed in which whether a pattern shape after the OPC or the PPC is appropriate is verified by OPC verification using a process simulation such as lithography and processing.
However, the OPC verification performs simulation such as lithography and processing and therefore takes a long time in the case of being performed on the whole integrated circuit pattern. Therefore, identical patterns are extracted from the integrated circuit pattern and the same simulation result is applied to the identical patterns. Thus, it is desired to determine whether a pattern shape is identical between patterns efficiently and accurately.